Method for designing a semiconductor device based on leakage current estimation

ABSTRACT

A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.

TECHNICAL FIELD

Embodiments of the disclosure relate to a method of designing asemiconductor device based on leakage current estimation.

BACKGROUND

A system-on-chip (SoC) includes several transistors. Two types ofvariations, for example global variations and local variations, leads toleakage in the transistors and hence to leakage in the SoC. The globalvariations are inter-die variations and affect integrated circuitdevices by causing differences in properties of circuit elementsfabricated on different chips (dies), albeit from the same wafer, ondifferent wafers, or on different batches of wafers. The localvariations, which are intra-die variations, are differences inelectrical properties that affect components of the integrated circuitsfabricated on one die. The local variations include systematicvariations and random variations. The systematic variations occur due tovariation in strength of an instrument used for manufacturing thetransistors. The random variations occur due to variation in number ofatoms that enter a channel while formation of the channel of thetransistors. It is desired to estimate the leakage of the SoC to manageand reduce the leakage, and in turn to improve power management of theSoC.

An existing technique for estimation of the leakage of the SoC includescorner based estimation technique. The manufacturing of the transistorscan result in three types of transistors, for example weak transistors,normal transistors and strong transistors, due to the global variations.The corner based estimation technique includes identifying a strongleakage corner for a strong transistor of the SoC. The strong leakagecorner can be defined as a process corner accounting for worst caseleakage of the strong transistor. Computation of the leakage for varioustransistors of the SoC is then performed for the strong leakage corner.The leakages of the cells can then be summed to determine the leakage ofthe SoC. However, the leakage of one transistor is independent of thatof another transistor and hence, computation of the leakage using thestrong leakage corner leads to a pessimistic estimation. Moreover, localvariations are not considered which may affect leakage of the SoC to acertain extent.

Another existing technique for estimation of the leakage of the SoCincludes a statistical analysis process of the SoC. The statisticalanalysis process includes performing several simulations which makes thestatistical analysis process computation intensive and in turn leads towastage of resources. Hence, there is a need for a method to design asemiconductor device based on leakage current estimation that considersboth local variations and global variations.

SUMMARY

An example of designing a semiconductor device includes preparing afirst design for the semiconductor device. The method also includesestimating leakage current for the first design. The method furtherincludes determining a leakage current cumulative distribution function(CDF) for the first design by calculating a plurality of mean shifts ofleakage current and a sum of the plurality of mean shifts, each meanshift of the plurality of mean shifts around a single global processcorner and a single operating voltage; by calculating the leakagecurrent at a plurality of global process points and at a plurality ofoperating voltages to obtain a global leakage current CDF; and byshifting each leakage current on the global leakage current CDF by thesum of the plurality of mean shifts to obtain the leakage current CDFfor the first design considering both global variations and localvariations and for the plurality of operating voltages. Further, themethod includes preparing a second design for the semiconductor devicebased on determination of the leakage current CDF for the first designand estimating leakage current for the second design. The method alsoincludes determining a leakage current CDF for the second design inaccordance to the determination of the leakage current CDF for the firstdesign. Moreover, the method includes selecting one of the first designand the second design based on a comparison of the leakage current CDFfor the first design and the leakage CDF for the second design.

Another example of a method of designing a semiconductor device includespreparing a first design for the semiconductor device and estimatingleakage current for the first design. The method also includesdetermining a leakage current cumulative distribution function (CDF) forthe first design by calculating a plurality of mean shifts of leakagecurrent, each mean shift of the plurality of mean shifts around aplurality of global process corners and a plurality of operatingvoltages to obtain a local variation mean shift; by calculating theleakage current at a plurality of global process points and at theplurality of operating voltages to obtain a global leakage current CDF;and by shifting each leakage current on the global leakage current CDFby the local variation mean shift to obtain the leakage current CDF forthe first design considering both global variations and local variationsand for the plurality of operating voltages. The method further includespreparing a second design for the semiconductor device based ondetermination of the leakage current CDF for the first design andestimating leakage current for the second design. Further, the methodincludes determining a leakage current CDF for the second design inaccordance to the determination of the leakage current CDF for the firstdesign. Moreover, the method includes selecting one of the first designand the second design based on a comparison of the leakage current CDFfor the first design and the leakage CDF for the second design.

An example of a method of estimating effects of local variations onleakage current for a semiconductor device includes statisticallyestimating a plurality of mean shifts of leakage current around a singleglobal process corner and a single operating voltage. The method alsoincludes calculating a sum of the plurality of mean shifts to estimate amean shift of the leakage current due to the local variations, the localvariations for the leakage current being determined based on a meanaround the single global process corner.

BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS

The drawings illustrate various embodiments and explain certain aspectsand advantages of the invention. They are illustrative only and are notto be taken as limiting the invention in any way. Like referencenumerals are used in the various drawings to refer to like elements.

FIG. 1 is an exemplary illustration of a transistor and leakageassociated with the transistor, in accordance with one embodiment;

FIG. 2 illustrates sensitivities of device leakage to processparameters, in accordance with one embodiment;

FIG. 3 illustrates standard deviation to mean for system-on-chip (SoC)leakage distribution as a function of number of transistors, inaccordance with one embodiment;

FIG. 4 illustrates an exemplary cell library, in accordance with oneembodiment;

FIG. 5 illustrates an exemplary tile, in accordance with one embodiment;

FIG. 6 is a graph illustrating percentage estimation error for apredicted worst case leakage compared to a statistical analysis, inaccordance with one embodiment;

FIG. 7 is an exemplary graph for a tile level mean mismatch shift acrossglobal process points, in accordance with one embodiment;

FIG. 8 is an exemplary graph illustrating a comparison of a globalleakage cumulative distribution function (CDF), an exact leakage CDF,and a modeled leakage CDF considering local variations, in accordancewith one embodiment;

FIG. 9 is an exemplary graph illustrating the mean shift in leakage withoperating voltage, in accordance with one embodiment;

FIG. 10 is a flowchart illustrating a method of designing asemiconductor device, in accordance with one embodiment; and

FIG. 11 is a flowchart illustrating a method of estimating effects oflocal variations on leakage current for a semiconductor device, inaccordance with one embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1 is an exemplary illustration of a transistor 105 and leakageassociated with the transistor 105. The leakage is represented asvarious leakage currents, for example a leakage current I1 to a leakagecurrent I6. The leakage current I1 is present due to reverse bias pnjunction leakage. A leakage current I2 is present due to subthresholdleakage. A leakage current I3 is present due to oxide tunneling. Aleakage current I4 is a gate current present due to hot-carrierinjection. A leakage current I5 is present due to gate-induced drainleakage (GIDL). The leakage current I6 is a channel punch throughcurrent.

As technology is down scaling, power consumption due to the leakage isincreasing as compared to power consumption happening due to switchingof the transistor 105. The leakage current I2 is an off state leakagefor current that flows between source and drain of the transistor 105when the transistor 105 has gate-source voltage below a certainthreshold. The leakage current I2 is becoming a dominant component ofthe leakage with the downscaling. The subthreshold leakage is sensitiveto process variations and depends on threshold voltage of the transistor105 as shown in equation (1).

I2=ae ^(k×f(V) ^(t) ^(L))  (1)

where a is a function of dimensions of the transistor 105 and othertechnology constants, k depends on geometry of the transistor 105, V_(t)is the threshold voltage of the transistor 105, L is length of thetransistor 105, and f(V_(t),L) is a linear function of V_(t) and L.

Hence, it is desired to estimate the leakage to manage power.

FIG. 2 illustrates sensitivities of device leakage to processparameters. More specifically, FIG. 2 illustrates a waveform 205corresponding to leakage current versus a waveform 210 corresponding toleakage delta as a function of threshold voltage V_(t), with thesubthreshold leakage (or off state leakage) depending strongly on V_(t).The leakage delta with respect to the leakage at change in V_(t)=0,illustrated with a waveform 215, increases exponentially with the changein V_(t). FIG. 2 thus illustrates that the subthreshold leakage variesexponentially with transistor length (L) and V_(t). As semiconductordevices are scaled down, supply voltage is lowered to reduce powerrequirements, which in turn further scales down V_(t) for maintaining areasonable gate over drive. To a second order, Vt depends on L due todrain induced barrier lowering (DIBL). DIBL refers to reduction of V_(t)of the transistor, for example the transistor 105, at higher drainvoltages and other effects.

Based on equation (1), it becomes apparent that the impact of localvariations on device leakage is significant, and therefore, should beconsidered for estimates of leakage for a particular design. Differentcells, for example a NAND gate and an inverter, have differentsensitivities to local variations, thus the consideration of localvariations is non-trivial to solve through a single global processcorner. A process corner refers to scope of parameter variations withinwhich an integrated circuit applied to a wafer must function properlyfor a particular design. On the other hand, a statistical analysis isoverly demanding in terms of computation time, complexity, andinfrastructure cost. In view of the above, the considering of localvariations in system-on-chip (SoC) level power-performance trade-offs isessential. The tradeoff analysis requires arriving at cumulativedistribution functions (CDFs) for performance and leakagesimultaneously. A CDF describes a statistical distribution which has avalue, at each possible outcome, of probability of having a leakagecurrent outcome or a lower leakage current outcome.

The method according to an embodiment of the present disclosureincorporates the impact of local variations in leakage estimates with acharacterization of mean shift in leakage due to mismatch around aglobal process corner. As a result, there is no analysis overhead at theSoC level since mean shifts of standard cells alone can be used tocompute worst case SoC leakage. According to another aspect, the presentdisclosure provides a framework for doing statisticalleakage-performance tradeoffs at the SoC level. The framework can beenabled through accurate CDF determination of the SoC leakage andenables tradeoffs of leakage and performance based on relationshipsbetween respective determined CDFs.

Thus, mismatch impact analysis proceeds from device level to the SoClevel. In an SoC, there are a multitude of independent leakagedistributions corresponding to each device of the SoC.

According to Lyapunov's extension to central limit theorem, summation ofa plurality of uncorrelated random variables tend to follow a Gaussiandistribution, with mean and sigma represented as in equation (2) givenbelow:

$\begin{matrix}{{\mu_{sum} = {\sum\limits_{i = 1}^{n}\mu_{i}}};{\sigma_{sum} = \sqrt{\sum\limits_{i = 1}^{n}\sigma_{i}^{2}}}} & (2)\end{matrix}$

where σ_(i) and μ_(i) are, respectively, standard deviation (sigma) andmean (mu) of n random variables.

Applying equation (2) for Lyapunov's extension to the leakage, it hasbeen determined that the mean shift of the SoC leakage due to localvariations equals the sum of the mean shifts of device leakagecharacterized around the global process corner. Mean of the SoC leakageincreases linearly with number of devices, whereas the sigma increasessub-linearly as the square root of sum of sigma is squared. In terms ofσ/μ, since a typical SoC includes multiple devices, σ/μ A shrinkssignificantly, allowing the leakage analysis to ignore the impactindividual device σ on overall SoC leakage.

FIG. 3 illustrates the sigma/mu (σ/μ) for SoC leakage distribution as afunction of number of transistors. To verify assumptions on σ/μ Ashrinking, an SoC scenario for FIG. 3 is mimicked with a collection oftransistors of various widths being chosen and with a mean mismatch (MM)analysis being done around a selected global 3-sigma corner. A graph 305in FIG. 3 illustrates σ/μ A of the SoC leakage distribution anddependency on a number of components. The SoC scenario confirms that σ/μA falls as 1/sqrt(n). For an SoC with over a million components, σ/μ Abecomes negligible, thereby quantifying the worst case leakage basedjust on the mean (μ).

A test case at the SoC level is described in conjunction with FIG. 4 andFIG. 5.

FIG. 4 illustrates an exemplary cell library 400, each cellcharacterized by corner leakage and MM impact. In one example, the celllibrary 400 includes 1× NAND gate 405 and the corner leakage (1 kg) andthe MM impact is included for the 1× NAND gate 405. Similarly, othercells in the cell library 400 are characterized by corner leakage and MMimpact. The cells in the cell library 400 can also be characterized atdifferent input states for which leakage and MM impact can vary.

FIG. 5 illustrates an exemplary tile 500 including a conglomeration ofvarious cells from the cell library, for example the cell library 400. Atile can be defined as a group of cells placed in a row and columnorder. A comparison is made of (1) the 3-sigma number resulting from astatistical analysis of local variations done by simulations, forexample Monte Carlo simulations, run on the SoC including approximately100,000 transistors with (2) added mean impact of the cells where thenumber of cells is a reduced sample set of approximately 1500 cells. Thecomparison is illustrated in FIG. 6.

FIG. 6 is a graph illustrating percentage estimation error for apredicted worst case leakage compared to the statistical analysis. Morespecifically, FIG. 6 shows an SoC level comparison of the methodaccording to an embodiment with an exemplary 1000 local variation MonteCarlo simulation. The axes include absolute leakage, number of tiles,and % error. The waveforms include a waveform 605 corresponding toglobal leakage, a waveform 610 corresponding to mean leakage, and awaveform 615 corresponding to the mean+3-sigma estimate of localvariations. The mean leakage can be defined as added mean impact forapproximately 1500 of the cells. The mean+3-sigma estimate of localvariations is based on the Monte Carlo simulation of the localvariations. The predicted worst case leakage and actual leakage(determined from the statistical analysis) are determined to beapproximately similar. An estimation error is determined from equation(3) to follow the sigma/mu relationship which is 1/sqrt(n).

Estimation error=8.6*(number of tiles)^(−0.46)  (3)

As illustrated by a waveform 620, the estimated error is below 1% whenthe number of tiles is 1000 or more. The convergence is furtherillustrated for mean impact based method to determine a statisticallyworst case SoC leakage.

In some embodiments, the worst case leakage CDF is obtained byperforming local variations Monte Carlo simulations. Alternatively,Latin Hypercube sampling (LHS) is used to obtain mean shift of the SoCleakage at each global point. LHS is a technique to generate statisticalvectors from a sample space, such that in a short number of vectors thesix sigma space, +/−3-sigma, can be covered. The present disclosure thusdescribes enabling choosing of a plurality of global points, and thecalculation of the impact on leakage due to local variations at each ofthe global points.

Another embodiment, described further below, establishes a fundamentalproperty of mean leakage shift at a global process point, enablingderivation of the mean leakage shift at another global process point tobe derived analytically.

The mean impact of mismatch on the leakage is independent of aparticular global process corner chosen. Hence, the mean impact at astrong corner is approximately similar to the mean impact at a typicalprocess corner.

The leakage can be expressed using an expression a*e^(kx), where x isthe threshold voltage V_(t), k is sensitivity of the transistor leakageto changes in threshold voltage V_(t) which depends on the geometry ofthe device, and a is a function of the dimensions and other technologyconstants of the transistor.

The mean leakage, after taking mismatch into consideration, can beanalytically derived. The global leakage is given as y=e^(kx). Assumingx₀ is the threshold voltage at a global process corner, and delta Δ is ashift in V_(t) around the global process corner due to mismatch:

$\begin{matrix}{{{Mean}\mspace{14mu} {Leakage}} = {{\frac{1}{2\nabla}{\int_{x_{0} - \Delta}^{x_{0} + \Delta}{^{kx}{x}}}} = {\frac{^{{kx}_{0}}}{2k\; \Delta}\left( {^{k\; \Delta} - ^{{- k}\; \Delta}} \right)}}} & (4)\end{matrix}$

Substituting equation (4) in equation (5), the shift in leakage can becalculated as given below:

$\begin{matrix}\begin{matrix}{{{Shift}\mspace{14mu} {in}\mspace{14mu} {leakage}} = \frac{{{Mean}\mspace{14mu} {leakage}} - {{Global}\mspace{14mu} {leakage}}}{{Global}\mspace{14mu} {leakage}}} \\{= \frac{{\frac{^{{kx}_{0}}}{2k\; \Delta}\left( {^{k\; \Delta} - ^{{- k}\; \Delta}} \right)} - ^{{kx}_{0}}}{^{{kx}_{0}}}} \\{= {\frac{1}{2k\; \Delta}\left( {^{k\; \Delta} - ^{{- k}\; \Delta} - {2k\; \Delta}} \right)}}\end{matrix} & \begin{matrix}\begin{matrix}\begin{matrix}\begin{matrix}(5) \\\;\end{matrix} \\(6)\end{matrix} \\\;\end{matrix} \\(7)\end{matrix}\end{matrix}$

The shift in leakage as given in equation (7) shows that percentagechange in the leakage depends only on k and Δ, as the global leakageitself is a function of x₀.

FIG. 7 is an exemplary graph for a tile level mean MM shift acrossglobal process points, for example 1000 global process points. The graphillustrates mean shift in leakage in percentage (%) versus globalprocess point's leakage. A waveform 705 corresponding to the mean shiftremains nearly constant for an entire process space from a corner 3 to acorner 1. The process space can be defined as a process spectrumcovering different variations within set bounds. A baseline 710identifies a 99.87 statistical global quantile point with MM. FIG. 7also illustrates corner invariance of mean shift on the tile for theentire process space from the corner 3 to the corner 1. Baselining withthe 99.87 statistical global quantile point and MM shift provides thecorner 1 being z % pessimistic, for example 16% pessimistic, the corner2 being y % pessimistic, for example 64% pessimistic, and a corner 4being x % pessimistic, for example 94% pessimistic, as compared to thebaseline 710. Pessimistic can be defined as over-prediction of theleakage at a corner, for example the corner 1, the corner 2, the corner3, and the corner 4.

Hence, the corner invariance of the mean shift in the leakage can beefficiently used to arrive at the leakage CDF. In addition, each globalprocess point in a leakage space can effectively see similar shift inleakage due to the local variations. The leakage space can be defined asa spectrum. The leakage space can also be inferred as a leakage graphwhere an X-axis is a global process point. Further, each process pointon the global leakage CDF can be shifted similarly, to arrive at a finalleakage CDF.

FIG. 8 is an exemplary graph illustrating a comparison of the globalleakage CDF, an exact leakage CDF, and a modeled leakage CDF consideringthe local variations. A waveform 805 corresponds to the global leakageCDF, a waveform 810 corresponds to the exact leakage CDF, and a waveform815 corresponds to the modeled leakage CDF. The exact leakage CDF isbased on local Monte Carlo simulations at each global process point.FIG. 8 includes an inset graph 820 with additional details from 2.00E-05global process point's leakage and higher. FIG. 8 further highlightsoverlay of modeled and determined CDF with actual and exact CDF obtainedthrough simulations at each global process point.

FIG. 9 is an exemplary graph illustrating the mean shift in leakage withoperating voltage. A global corner CDF 915 is shown along with a meanshifted CDF 910 after the mean shift is applied to the global cornerCDF. A waveform 905 corresponds to the mean shift in leakage andillustrates invariance of the mean shift leakage to the operatingvoltage.

FIG. 10 is a flowchart illustrating a method of designing asemiconductor device.

At step 1005, a first design is prepared for the semiconductor device,for example a system on chip (SoC).

At step 1010, leakage current is estimated for the first design. Theleakage current is estimated by statistically characterizing a mismatchimpact on leakage for each cell of a plurality of cells of thesemiconductor device through a number of simulations, for example MonteCarlo simulations, applied to a reduced sample set. Mean of the mismatchimpact for each cell is then added. The leakage current is furthergenerated for the semiconductor device.

In some embodiments, the number of simulations can be reduced. In oneexample a sampling method, Latin Hypercube Sampling (LHS), can befurther used to reduce the number of Monte Carlo simulations.

At step 1015, a leakage current cumulative distribution function (CDF)is determined for the first design. The determination of the leakage CDFis given below.

A plurality of mean shifts of leakage current and a sum of the pluralityof mean shifts is calculated. Each mean shift of the mean shifts isaround a single global process corner and a single operating voltage.Each mean shift is further invariant of the operating voltage. Thesingle global process corner includes a corner exhibiting one of desiredperformance and undesired leakage.

In some embodiments, only the mean shifts of leakage current arecalculated. Each mean shift is around a plurality of global processcorners and a plurality of operating voltages to obtain a localvariation mean shift. The global process corners can range from five toten global process corners.

The leakage current at a plurality of global process points and at aplurality of operating voltages is then calculated to obtain a globalleakage current CDF.

Each leakage current on the global leakage current CDF is furthershifted by the sum of the mean shifts to obtain the leakage current CDFfor the first design considering both global variations and localvariations and for the operating voltages.

In some embodiments, each leakage current on the global leakage currentCDF is shifted by the local variation mean shift. The local variationmean shift can be obtained by linear approximation, for examplepiecewise linear approximation.

At step 1020, a second design is prepared for the semiconductor devicebased on determination of the leakage current CDF for the first design.

At step 1025, leakage current is estimated for the second design. Theleakage current for the second design is estimated by statisticallycharacterizing a mismatch impact on leakage for each cell of a pluralityof cells of the semiconductor device through a number of simulations,for example Monte Carlo simulations, applied to a reduced sample set.Mean of the mismatch impact for each cell is then added. The leakagecurrent is further generated for the semiconductor device.

At step 1030, a leakage current CDF is determined for the second designin accordance to the determination of the leakage current CDF for thefirst design.

At step 1035, one of the first design and the second design is selectedbased on a comparison of the leakage current CDF for the first designand the leakage CDF for the second design. The selection is performed bycalculating a performance CDF and tradeoffs between leakage andperformance. The selection further enables a tradeoff analysis betweenleakage and performance using the leakage current CDF in conjunctionwith a performance CDF.

The semiconductor device is further manufactured according to one of thefirst design and the second design.

FIG. 11 is a flowchart illustrating a method of estimating effects oflocal variations on leakage current for a semiconductor device.

At step 1105, a plurality of mean shifts of leakage current arestatistically estimated around a single global process corner and asingle operating voltage. The estimating includes statistical modelingof a mismatch impact on leakage for each cell of the semiconductordevice through a plurality of simulations applied to a reduced sampleset. In one example, the simulations can be Monte Carlo simulations andthe reduced sample set includes lesser than 1500 samples.

At step 1110, a sum of the mean shifts is calculated to estimate a meanshift of the leakage current due to the local variations. The localvariations for the leakage current are determined based on a mean aroundthe single global process corner.

The estimation of the leakage current accounts for both local variationsand global variations and provides better accuracy in results.

The foregoing description sets forth numerous specific details to conveya thorough understanding of embodiments of the disclosure. However, itwill be apparent to one skilled in the art that embodiments of thedisclosure may be practiced without these specific details. Somewell-known features are not described in detail in order to avoidobscuring the disclosure. Other variations and embodiments are possiblein light of above teachings, and it is thus intended that the scope ofdisclosure not be limited by this Detailed Description, but only by theClaims.

1. A method of designing a semiconductor device, the method comprising: preparing a first design for the semiconductor device; estimating leakage current for the first design; determining a leakage current cumulative distribution function (CDF) for the first design by: calculating a plurality of mean shifts of leakage current and a sum of the plurality of mean shifts, each mean shift of the plurality of mean shifts around a single global process corner and a single operating voltage; calculating the leakage current at a plurality of global process points and at a plurality of operating voltages to obtain a global leakage current CDF; and shifting each leakage current on the global leakage current CDF by the sum of the plurality of mean shifts to obtain the leakage current CDF for the first design considering both global variations and local variations and for the plurality of operating voltages; preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design; estimating leakage current for the second design; determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design; and selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.
 2. The method as claimed in claim 1, wherein estimating the leakage current comprises: statistically characterizing a mismatch impact on leakage for each cell of a plurality of cells of the semiconductor device through a number of simulations applied to a reduced sample set; adding mean of the mismatch impact for each cell of the plurality of cells; and generating the leakage current for the semiconductor device.
 3. The method as claimed in claim 2 and further comprising reducing the number of simulations.
 4. The method as claimed in claim 3, wherein a sampling method is used to reduce the number of simulations.
 5. The method as claimed in claim 1, wherein the semiconductor device comprises a system-on-chip.
 6. The method as claimed in claim 3, wherein each mean shift of the plurality of mean shifts of the leakage current is invariant of the operating voltage.
 7. The method as claimed in claim 6, wherein the single global process corner comprises a corner exhibiting one of desired performance and undesired leakage.
 8. The method as claimed in claim 7, wherein selecting one of the first design and the second design further comprises calculating a performance CDF, and tradeoffs between leakage and performance.
 9. The method as claimed in claim 8 and further comprising manufacturing the semiconductor device according to one of the first design and the second design.
 10. A method of designing a semiconductor device, the method comprising: preparing a first design for the semiconductor device; estimating leakage current for the first design; determining a leakage current cumulative distribution function (CDF) for the first design by: calculating a plurality of mean shifts of leakage current, each mean shift of the plurality of mean shifts around a plurality of global process corners and a plurality of operating voltages to obtain a local variation mean shift; calculating the leakage current at a plurality of global process points and at the plurality of operating voltages to obtain a global leakage current CDF; and shifting each leakage current on the global leakage current CDF by the local variation mean shift to obtain the leakage current CDF for the first design considering both global variations and local variations and for the plurality of operating voltages; preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design; estimating leakage current for the second design; determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design; and selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.
 11. The method as claimed in claim 10, wherein estimating the leakage current comprises: statistically characterizing a mismatch impact on leakage for each cell of a plurality of cells of the semiconductor device through a number of simulations applied to a reduced sample set; adding mean of the mismatch impact for each cell of the plurality of cells; and generating the leakage current for the semiconductor device.
 12. The method as claimed in claim 11, wherein the local variation mean shift is obtained by linear approximation.
 13. The method as claimed in claim 11, wherein the plurality of global process corners ranges from five to ten global process corners.
 14. The method as claimed in claim 11, wherein the semiconductor device comprises a system-on-chip.
 15. The method as claimed in claim 11, wherein selecting one of the first design and the second design further comprises enabling a tradeoff analysis between leakage and performance using the leakage current CDF in conjunction with a performance CDF.
 16. The method as claimed in claim 11 and further comprising manufacturing the semiconductor device according to one of the first design and the second design.
 17. A method of estimating effects of local variations on leakage current for a semiconductor device, the method comprising: statistically estimating a plurality of mean shifts of leakage current around a single global process corner and a single operating voltage; and calculating a sum of the plurality of mean shifts to estimate a mean shift of the leakage current due to the local variations, the local variations for the leakage current being determined based on a mean around the single global process corner.
 18. The method as claimed in claim 17, wherein statistically estimating the plurality of mean shifts comprises statistically modeling a mismatch impact on leakage for each cell of the semiconductor device through a plurality of simulations applied to a reduced sample set.
 19. The method as claimed in claim 18, wherein the plurality of simulations are Monte Carlo simulations.
 20. The method as claimed in claim 18, wherein the reduced sample set comprises lesser than 1500 samples. 